ld	bc,adr1		; BC:=ADR1;
loop:	in	a,(ctl)
	and	status		; loop waiting for data ready for output;
	jp	nz,loop
	ld	a,(bc)		; A:=BC;
	out	(data),a	; Output data;
	ld	hl,-adr2	; HL:=(-ADR2);
	add	hl,bc		; HL:=HL+BC;
	inc	bc		; BC:=BC+1;
	jp	nc,loop		; go to LOOP if address in BC register pair less
				;       than ADR2;


adr1	equ	$		; starting address;
	ds	10		; define storages area;
adr2	equ	$		; ending address;
ctl	equ	2		; equate CTL to 2;
data	equ	ctl+1		; eqate DATA to CTL+1;
status	equ	80h		; equate STATUS to bit pattern to be compared
				;           from input port;