LXI	B,ADR1		; BC:=ADR1;
LOOP:	IN	CTL
	ANI	STATUS		; loop waiting for data ready for output;
	JNZ	LOOP
	LDAX	B		; A:=BC;
	OUT	DATA		; Output data;
	LXI	H,-ADR2		; HL:=(-ADR2);
	DAD	B		; HL:=HL+BC;
	INX	B		; BC:=BC+1;
	JNC	LOOP		; go to LOOP if address in BC register pair less
				;       than ADR2;


ADR1	EQU	$		; starting address;
	DS	10		; define storages area;
ADR2	EQU	$		; ending address;
CTL	EQU	2		; equate CTL to 2;
DATA	EQU	CTL+1		; eqate DATA to CTL+1;
STATUS	EQU	80H		; equate STATUS to bit pattern to be compared
				;           from input port;